The present invention relates to dynamic random access memory circuits and particularly to equalizing circuits in dynamic random access memory circuits.
Dynamic random access memory (DRAM) circuits are known. In a DRAM circuit, there may be millions, even billions, of memory cells. The memory cells are typically grouped in a plurality of memory arrays, each of which contains a subset of the total number of memory cells of the DRAM circuit. By way of example, a 256 Megabit DRAM cell may have up to 256 arrays, each of which may contain roughly 1-megabit of DRAM cells. The arrays may be arranged in rows and columns, e.g., 32.times.8 in one example.
The memory cells in each array are also arranged in rows and columns for ease of access. A plurality of bit lines and word lines are then employed to read from and/or write to each memory cell. For ease of discussion, the bit lines may be thought of as being in the vertical direction although bit lines may be either vertical or horizontal, with the word lines disposed orthogonal to the bit lines.
A column of memory cells is generally coupled to a pair of bit lines. During the active cycle of the DRAM, information may be written to or read from the cells through the bit lines. The bit lines are typically complementary, with one bit line low and the other bit line high during reading or writing. By way of example, if the DRAM operates on 3V, the voltages on the bit lines are typically 0V and 3V during a given active cycle.
During the inactive cycle, the bit lines are precharged in preparation for the next active cycle. Precharging equalizes the voltages on the pair of bit lines to a predetermined voltage level, which typically is about 1/2of the "high" voltage level. Using the previous example, the voltages on the pair of bit lines may be precharged to, for example, 1.5 V in preparation for the next active cycle.
To facilitate discussion, FIG. I illustrates an exemplary prior art equalizer circuit 100 employed to precharge the bit lines. As shown, the circuit is coupled to bit lines 102a and 102b from array 104. Bit lines 102a and 102b, as mentioned before, are complementary of one another. During the inactive cycle, a signal EQ on conductor 106 turns on switch 108 (typically an n-FET device) to short bit lines 102a and 102b together to substantially equalize their voltages. The same signal EQ also turns on switch 110, which is typically an n-FET device that is coupled to bit line 102a, to supply a precharge potential level VBLEQ to bit line 102a. The same signal EQ also turns on switch 112, which is typically an n-FET device that is coupled to bit line 102b, to supply a precharge potential level VBLEQ to bit line 102b. By turning on all these three switches 108, 110, and 112 simultaneously, the voltages on bit lines 102a and 102b are equalized and precharged to the precharge potential level VBLEQ during the DRAM inactive cycle. Since all three switches 108, 110, and 112 participate in equalizing the bit lines, they are referred to herein as the set of three equalizing switches.
Precharge potential level VBLEQ is supplied to the aforementioned switches 110 and 112 through an optional current limiting switch 114. Switch 114 is typically an n-FET depletion device that has its gate and source coupled together. Accordingly, switch 114 is normally "on" and VBLEQ is always supplied to switches 110 and 112 (the bit lines themselves do not receive VBLEQ until switches 110 and 112 are turned on, as discussed earlier). If a column of cells is defective (e.g., either bit line 102a or 102b is shorted to ground), switch 114 prevents the defect from drawing down the voltage level of VBLEQ excessively and from rendering the entire DRAM unusable. The defective column of cells may then be replaced by a redundant column of cells using standard replacement techniques.
FIG. 2 is a layout view of equalizer circuit 100 of FIG. 1, including bit lines 102a and 102b. In FIG. 2, three layers are shown: a metal layer, a polysilicon layer, and an active layer. The metal layer is employed for implementing the bit lines and some interconnect. The metal layer overlies a polysilicon layer and is insulated therefrom by a layer of dielectric. The polysilicon layer is employed to implement gates of the switches and to provide conduction among some switches. The polysilicon layer overlaps an underlying active layer in some places to form n-FET switches. The functions of the devices of FIG. 2 are more fully discussed in the explanation that follows.
Signal EQ of FIG. 1 is provided on metal line 200. Through contact 202, signal EQ is also provided to polysilicon conductor 204. Polysilicon conductor 204 furnishes the gates for switches formed where polysilicon conductor 204 overlies an underlying active layer 206. As polysilicon conductor 204 overlies active layer 206 in multiple places, multiple switches are formed.
Switch 108 of FIG. 1 is formed where polysilicon area 204a overlaps active areas 206a and 206b. As can be seen in FIG. 2, polysilicon area 204a is disposed in the vertical portion of the T-shaped polysilicon gate portion 204TA. Switch 110 of FIG. 1 is formed where polysilicon area 204b overlaps active areas 206c and 206d. As can be seen in FIG. 2, polysilicon area 204b is disposed in the horizontal portion of the T-shaped polysilicon gate portion 204TA. Switch 112 of FIG. 1 is formed where polysilicon area 204c overlaps active areas 206e and 206f. As can be seen in FIG. 2, polysilicon area 204b is disposed in the other horizontal portion of the T-shaped polysilicon gate portion 204TA. Polysilicon areas 204a, 204b, and 204c of polysilicon conductor 204 make up the T-shaped polysilicon gate portion 204TA that forms switches 108, 110, and 112. For ease of reference, this polysilicon conductor is referred herein as T-shaped polysilicon gate portion 204TA (to distinguish it from the T-shaped polysilicon gate portion 204TB of the adjacent bit line pairs).
Active area 206a of switch 108 is coupled to bit line 102a through contact 220. Active area 206b of switch 108 is coupled to bit line 102b through contact 222. When the EQ signal is present on polysilicon conductor 204 (and therefore polysilicon area 204a), a conductive channel is created between active areas 206a and 206b of switch 108, thereby shorting together bit lines 102a and 102b in the manner discussed in connection with FIG. 1.
The presence of the EQ signal on polysilicon conductor 204 also causes this same signal to be present on polysilicon area 204b, thereby creating a conductive channel between active areas 206c and 206d, i.e., turning on switch 110. Likewise, the presence of the EQ signal on polysilicon conductor 204 also causes this same signal to be present on polysilicon area 204c, thereby creating a conductive channel between active areas 206e and 206f, i.e., turning on switch 112.
Active areas 206e and 206d, being in the same active area layer, are interconnected. This interconnection represents connector 120 of FIG. 1, i.e., the connector that couples switches 110 and 112 to VBLEQ (via switch 114). In FIG. 2, this interconnection is coupled to active area 206g of switch 114. A polysilicon gate area 230(a) of polysilicon line 230 serves as a gate for switch 114. This polysilicon layer 230 also couples through contact 234 with metal line 232, which is in turn coupled to the interconnection of active areas 206d/206e through contacts 236a and 236b. Metal line 232 therefore couples the gate of switch 114 to its source in the manner shown in FIG. 1. Normally, this source-to-gate connection permits switch 114 to remain on, i.e., to permit a conductive channel to exist between active areas 206g and 206h of switch 114.
Active area 206h is coupled in the active area layer to metal 240, which carries the VBLEQ signal. Thus the VBLEQ signal is supplied from metal 204 to switches 110 and 112 through switch 114. One skilled in the art would readily appreciate the correspondence between the elements of diagramatic FIG. 1 and of layout FIG. 2.
In FIG. 2, the area required to implement the equalizer circuit is bounded roughly within the area delineated by arrows X and Y. In a typical 256M-bit DRAM, for example, there may be up to 4000 bit line pairs in each array. To maximize the area available for implementing the equalizer circuits, designers have in the past interleaved the bit line pairs. By interleaving, the odd bit line pairs may be equalized with equalizer circuits provided at, for example, the upper edge of the array while the even bit line pairs may be equalized with equalizer circuits provided at, for example, the lower edge of the array.
FIG. 3 depicts a hypothetical array 300 to illustrate this interleaving concept. In array 300, odd bit line pairs 301 and 303 extend out from upper edge 320 to be equalized with equalizer circuits 322 and 324 provided within equalizer strip 326. Likewise, even bit line pairs 302 and 304 extend out from lower edge 350 to be equalized with equalizer circuits 352 and 354 provided within equalizer strip 356. By interleaving the bit line pairs, there is more area to implement the equalizer circuits within the equalizer strips, e.g., equalizer circuit 322, 324, 352, or 354, than if all the bit lines simple extended out of one of edges 320 and 350 of array 300.
Referring back to FIG. 2, it has been found that the X dimension of the equalizer circuit is typically predefined by the dimension of the design rules employed to fabricate the memory cells within the array. Accordingly, when the design rules for the array changes, the bit lines are spaced closer, which reduces the area available for implementing the equalizer circuit. By way of example, when the design rules within the array change from 0.25 micron to 0.175 micron, e.g., in the case of 1-Gigabit DRAM circuits, the X dimension available for implementing each equalizer circuit may be reduced to only, for example, 0.5 micron.
Although the design rules within the array may shrink, it has also been found that photolithography and design constraints prevent the designer from using correspondingly aggressive, i.e., small design rules, in the implementation of the equalizer circuits. This is due, in part, to the fact that the memory cells within the array are highly regular and repeatable and are therefore more suitable for the smaller design rules than those outside of the array.
As can be expected, the differential between the design rules employed inside the array and those employed outside the array gives rise to design difficulties. Consider the situation wherein the design rules inside the array is shrunk so that they are substantially smaller than those employed outside the array. Since the distance between adjacent bit line pairs shrink, e.g., between bit line pairs 301 and 303 of FIG. 3, less area is available for implementing the equalizer circuits outside of the array (as the term is used herein, "adjacent bit line pairs" refer to bit line pairs that are adjacent to one another on one side of the array). Unless an improved equalizer circuit design is found, it may no longer be possible to, for example, place the T-shaped polysilicon gate portions of adjacent equalizer circuits (e.g., T-shaped polysilicon gate portion 204TA and T-shaped polysilicon gate portion 204TB of FIG. 2) adjacent to one another along a row in the equalizer strip since the spacings between adjacent bit line pairs may be too small for such placement.
In view of the foregoing, there are desired improved equalizer circuit designs and methods therefor that advantageously reduce the area required for implementing the equalizer circuit.